A pin grid array package of the prior art can have pins 2A-2K (FIG. 1A) that are straight and that pass through a substrate 1 (as described at col. 2, line 66 to col. 3, line 29 of U.S. Pat. No. 5,538,433 granted to Arisaka).
Another pin grid array package 10 (FIG. 1B) disclosed by U.S. Pat. No. 5,403,784 granted to Hashemi et al. (hereinafter the "Hashemi Patent") supports a die 11 that is connected by bond wires 12A-12K to a corresponding number of leads 13A-13K included in package 10. Leads 13A-13K are portions of leadframes that are bonded (col. 1, lines 53-55 and col. 2, lines 31-32) to a "template" 14 (col. 8, line 56) by one or more insulation layers 14A-14C (also called "castellated seal rings" at col. 8, line 53). Each of leads 13A-13K is of a unitary construction that is "bent" (see col. 5, line 58) into an "L" shape, with a first leg attached to a layer 14I and a second leg passing through substrate 14 to protrude into a region 15 on the exterior of package 10.